Verilog On Linux: Defenestrating Modelsim
Defenestrate /diˈfɛnəˌstreɪt/ (verb) : to throw (a person or thing) out of a window. The word originated from a couple of incidents in Prague, back in the 14th century, when a bunch of guys stormed in and tossed seven town officials out the window (quite literally).
This tutorial’s to the victims of the Modelsim user experience, forced to design hardware in chains and gracefully handle the precious rear end of the popular musty racehorse that’s Mentor Graphics’ stable-star. If you’re on Linux, freedom’s a nice option.
I’ll walk you through the steps to start coding in Verilog on your Linux box:
Install the simulator and graphing tools
Save the following code out into two files:
Compile and run the code
Open a terminal in the same directory and compile the code with this command:
Run the code with this command:
Simulate the generated output with this:
gtkwave test.vcd &
test on the top-left panel and select
c1, then drag the signals from the
bottom-left (wire, reg) to the Signals panel to it’s immediate right. This should get
you out on the right side of the bed with Verilog on Linux. Your next steps lie
here. All sample code and instructions are merely distilled
from the extensive documentation at the wiki linked to above.